Device isolation techniques play an important role in the design and performance of highly integrated semiconductor circuits by electrically isolating regions and devices therein from adjacent devices and regions. Moreover, as the degree of integration in semiconductor circuits increases, there is a concomitant need to develop techniques for forming isolation regions which are free of defects and can be scaled to provide isolation regions having smaller dimensions, but without sacrificing the isolation capability of the regions.
One widely used and relatively simple technique for providing device isolation is typically referred to as local oxidation of silicon (LOCOS). Unfortunately, this technique has a number of disadvantages because it typically includes the formation of bird's beak oxide extensions, induces lattice stress which can lead to the formation of crystal defects in semiconductor substrates, and causes redistribution of channel-stop dopants. As will be understood by those skilled in the art, these disadvantages typically cause a reduction in the lateral area available for active devices, and degrade the reliability and performance of devices formed in adjacent active regions.
Another method which may be considered an improvement over the LOCOS method is typically referred to as the shallow trench isolation (STI) method. In the STI method, a device isolation region is established by selectively etching a semiconductor substrate to form trenches therein and then filling the trenches with an electrically insulating region (e.g., oxide). A chemical etching and/or chemical-mechanical polishing (CMP) step can then be performed to planarize the electrically insulating region to be level with the surface of the substrate. Because the STI method typically does not include a lengthy thermal oxidation step as typically required by the LOCOS method, many of the disadvantages of the LOCOS method can be eliminated to some degree. However, as will be understood by those skilled in the art, the STI method may be prone to a "dishing" phenomenon which can degrade the isolation characteristics of trench isolation regions.
Hereinafter, a conventional trench isolation method for a semiconductor device will be described with reference to FIGS. 1 through 6. First, referring to FIG. 1, a pad oxide layer 12 and a nitride layer 14 are deposited on a semiconductor substrate 10 in sequence. The pad oxide layer 12 functions as a protection layer for an active region during the formation of a trench. Then, a photoresist pattern 16, for defining a region in which the trench is to be formed, is formed on the nitride layer 14. Then, as shown in FIG. 2, the nitride layer 14 and the pad oxide layer 12 are etched in sequence using the photoresist pattern 16 as an etching mask to form a nitride layer pattern 14A and a pad oxide layer pattern 12A. Then, the semiconductor substrate 10 is dry-etched to form a trench 17 with a predetermined depth. Next, as shown in FIG. 3, after removing the photoresist pattern 16, an oxide layer 18 is formed on the nitride layer pattern 14A with a predetermined thickness while completely filling the trench 17, using a chemical vapor deposition (CVD) method.
Then, as shown in FIG. 4, the oxide layer 18 is planarized by a chemical mechanical polishing (CMP) process, using the surface of the nitride layer pattern 14A as a planarization stop, to form a field oxide layer pattern 18A. Thereafter, as shown in FIG. 5, the nitride layer pattern 14A and the pad oxide layer pattern 12A are removed to define the trench isolation region 18A. Then, a sacrificial oxidation process and a cleaning process are performed to complete a trench isolation region 18B as shown in FIG. 6.
However, according to the conventional trench isolation method, the edge portion of the oxide layer filling the trench is also etched by the sacrificial oxidation process or the cleaning process, showing a profile such as portion "A" shown in FIG. 6. That is, the device isolation region is slanted at the upper boundary between the active region and the device isolation region, so that a gate oxide layer becomes thinner at the boundary and an electric field is concentrated thereon. Also, stress may be applied to an upper insulation region to be formed in a following step. This stress can promote the generation of leakage currents and otherwise deteriorate the characteristics of the devices formed in adjacent active regions.
Thus, notwithstanding the above described methods, there continues to be a need for improved methods of forming field oxide isolation regions which are compatible with very large scale integration (VLSI) processing techniques.